vaah
Member level 3
Hi guys,
I have a simple code and I want to simulate it in cadence but I'd rather not use Verilog-A. I appreciate your thoughts and comments if anything crosses your mind!
Also, during the simulation, if one time "VDC=2" happens I don't want it to change "VDC" anymore.
Thank you.
I have a simple code and I want to simulate it in cadence but I'd rather not use Verilog-A. I appreciate your thoughts and comments if anything crosses your mind!
Code:
if ((V(WL)-Vth)>0) VDC=2;
else VDC = 0;
Also, during the simulation, if one time "VDC=2" happens I don't want it to change "VDC" anymore.
Thank you.