
You don't instantiate the modules in the case statement, can't be done the language doesn't allow this. So get that out of your head. You're obviously thinking like a software programmer, where you can call some function in a case statement.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 // instantiated add module ADD ADD_inst ( .A (a_data), .B (b_data), .A_PLUS_B (output_bus_of_your_add_module) ); // case statement is wrapped in some always block, (not shown) case (alu_sel) `ALU_ADD : alu_result <= output_bus_of_your_add_module; `ALU_SUB : alu_result <= output_bus_of_your_sub_module; `ALU_SHL : alu_result <= output_bus_of_your_shift_left_module; //etc.... endcase