buenos
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hi
how do you guys control net segment lengths for compley net topologies in altium designer?
What i found is that it supports only total etch length control, and that is it.
The cadence allegro supports segment length nicely. the most advanced way in allegro is to select a net, export it to the signal explorer topology viewer, set up what topology we want, and whats are the segment lengths (min/max, or relative to each other in signal groups) in that.
i have not seen anything like that in altium.
for simple microcontroller boards it is not a problem, but for example if you want to design a jedec Jesd21C based DDR3 memory-down layout, i have a feeling that it is not possible with altium at all.
how would you implement these in altium?
1.) DDR3 memory-down, based on SODIMM standard: www.jedec.org > (log in) > free standards > DDR1/2/3 > jesd21C files > JESD21-C > all of document > MODULE4_20_18
2.) Compact PCI host card: lengths between: cPCI connector to series resistor, series resistor to pullup, pullup stub, cpci connector to interface chip. On a host board, the clocking nets also have a complicated topology. if you have picmg2.0 spec, you can check the details.
3.) Intel chipset FSB: matched groups, where each signal has a package length which will be an offset in length matching. check this: https://www.intel.com/Assets/PDF/designguide/252614.pdf page 43.
we use Allegro, but it would be nice to use Altium, since its easier to create designs with that, and more enjoyable. without these features i could not use Altium in my work, unfortunatelly. There are hundreds of segmenth-length-controlled signals on evey board we design...
how do you guys control net segment lengths for compley net topologies in altium designer?
What i found is that it supports only total etch length control, and that is it.
The cadence allegro supports segment length nicely. the most advanced way in allegro is to select a net, export it to the signal explorer topology viewer, set up what topology we want, and whats are the segment lengths (min/max, or relative to each other in signal groups) in that.
i have not seen anything like that in altium.
for simple microcontroller boards it is not a problem, but for example if you want to design a jedec Jesd21C based DDR3 memory-down layout, i have a feeling that it is not possible with altium at all.
how would you implement these in altium?
1.) DDR3 memory-down, based on SODIMM standard: www.jedec.org > (log in) > free standards > DDR1/2/3 > jesd21C files > JESD21-C > all of document > MODULE4_20_18
2.) Compact PCI host card: lengths between: cPCI connector to series resistor, series resistor to pullup, pullup stub, cpci connector to interface chip. On a host board, the clocking nets also have a complicated topology. if you have picmg2.0 spec, you can check the details.
3.) Intel chipset FSB: matched groups, where each signal has a package length which will be an offset in length matching. check this: https://www.intel.com/Assets/PDF/designguide/252614.pdf page 43.
we use Allegro, but it would be nice to use Altium, since its easier to create designs with that, and more enjoyable. without these features i could not use Altium in my work, unfortunatelly. There are hundreds of segmenth-length-controlled signals on evey board we design...