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hi guys,
I assign pin assignment for Altera FPGA Cyclone IV then this Error Message occur:
Error: Cannot place pin ovMemBa[0] to location B3
Error: Can't place VREF pin B5 (VREFGROUP_B8_N1) for pin ovMemBa[0] of type output with SSTL-18 Class I I/O standard at location B3
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 8 when the VREF pin B5 (VREFGROUP_B8_N1) is used on device EP4CE55F23C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 9 pin(s) are placed
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location (pad PAD_376): unused
Info: Location (pad PAD_377): unused
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location B3 (pad PAD_379): unused (but has pin assignment of ovMemBa[0])
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard
all problem posted in the internet(with same error message) is because of bidirectional signal but in my problem all locations are assigned as output. do anyone has any idea how to solve this problem?
I assign pin assignment for Altera FPGA Cyclone IV then this Error Message occur:
Error: Cannot place pin ovMemBa[0] to location B3
Error: Can't place VREF pin B5 (VREFGROUP_B8_N1) for pin ovMemBa[0] of type output with SSTL-18 Class I I/O standard at location B3
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 8 when the VREF pin B5 (VREFGROUP_B8_N1) is used on device EP4CE55F23C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 9 pin(s) are placed
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location (pad PAD_376): unused
Info: Location (pad PAD_377): unused
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location B3 (pad PAD_379): unused (but has pin assignment of ovMemBa[0])
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard
all problem posted in the internet(with same error message) is because of bidirectional signal but in my problem all locations are assigned as output. do anyone has any idea how to solve this problem?