altera constrains quartus

[treqer]

whether you want to describe the input clock, or rather that its value is specified as the input frequency to describe the unit PLL?

---------- Post added at 09:24 ---------- Previous post was at 08:19 ----------

Clarify. In xilinx ample set the input frequency of DCM in UCF. In this case, all produced by it. clock constraints are assigned automatically. Holds it for Altera? I point out the input pin in assigment and say 50 mhz. Will be created clock constraints for all PLL outputs?

 

[FvM]

Will be created clock constraints for all PLL outputs?

Basically, yes.

 

[alledauser]

You can create a clock within TimeQuest. Constraints->Create Clock.
If the clock is the reference to a PLL, it is automatically recognized .
Include "derive_pll_clocks -create_base_clocks" command in your sdc file to define pll outputs as clocks.
Frequencies of PLL output signals are calculated automatically.

 

[treqer]

project not content *.sdc file. create?
how to get this entry through the quartus interface?

if i create new assigments for PLL out clk's, derived input clk (proj//setting//individual clock//new//baset on ) it will be properly ?