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AHB bus error response

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dpaul

dpaul

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I am trying to understand how an AHB error response works and have some questions.

The following is an excerpt from the spec.
IDjedMzLrebhPRCPSaYvqbEV


What is meant here by "error has occured during the transfer"?

I have two use cases in mind:
1. Can an AHB slave signal an error response to the master, when the master tries to write to a read-only memory location within a slave?
2. Can an AHB slave signal an error response to the master (consider 1 M and 1 S scenario), when the master tries to access an invalid slave memory location?

Please enlighten me with the scenarios which can lead the slave in driving the HRESP high.
 
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