Again about Common Mode Input Range

[sjamil02]

Hi all,

I simulated a differential amplifier (nmos input transistor and current mirror load) with all the transistor aspect ratio 1 (3um/3um). When running dc analysis, the common mode voltage range is the maximum voltage limit Vicmax where input transistor starts to go into triode and the minimum voltage limit Vicmin that keeps tail transistor in saturation. (see attachment). Also from the graph within the common mode range voltage, ideally VOUT should be zero, but i got around ~500mV, so I say common mode offset is 500mV? Anybody can help with the equation to calculate common mode offset?-->

Next, I determined from simulation(graph in the attachment) that Vinmin and Vinmax is 1.4V and 1.7V. Does this means that for the proper operation and highest gain, the input common mode voltage must be within this range say 1.5V? And if it is out of this range, the differential gain is small or is not constant.??

I also determined the gain from Vout vs. Vin transfer curve. Take the gradient (x2-x1/y2-y1) around 0v input. I got around 0.2. I verified this in ac simulation.
(1) The input common voltage at 1.5v and Ac=1. Is this correct? The result does not quite match with the gain obtained from dc analysis.
(2)I tried with 0v common mode and Ac=1, the result quite match with dc analysis. Now here i get confused.
Why (2) is much closer to gain obtained from dc analysis? In this case common mode voltage is 0v, is it not out of range?

Appreciate comments.

cheers
sj

 

[sjamil02]

Hellow all,

I'm still waiting for reply. Any thought or comment is appreciated.

cheers
sj

 

[doibongvui]

Hi
It is difficult to read your picture. Can you show us your schematic? We can analyze from it. Thanks

 

[keith1200rs]

I don't think joining the inverting & non-inverting inputs of an opamp is the correct way to determine common mode range. I would suggest trying to connect it as a simple buffer and sweeping the non-inverting input. Even so, that wouldn't isolate input range from output range.

Keith.

 

[sjamil02]

Sorry my previous attachment was not clear. Here's the attachment again.

Basically I was trying to double confirm what I did was right.

I ran a basic diff amp as shown in the attachment to determine and understand the common mode input voltage range ICMR.

In PE Allen & Holberg book (pp 186). " The way that ICMR is found is to set differential input voltage to zero and vary common input voltage until one of the transistor in the diff amp no longer saturate"

So the minimum range VICMIN is where the tail transistor M3 started to saturate (VDSsat_m3 => VGm3-Vth). The maximum range VICMAX is where the input transistor M4 started to be in triode (0 < VDS_m4 < VGm3-Vth). You can see the waveform from the attachment. From the graph, ICMR is 1.4V - 1.7V. Is this correct?

Now to determine the common mode gain Avcm, I measured the gradient of output signal (y2-y1/x2-x1) at the ICMR range (1.4V-1.7V). Is this the correct way to measure gain in dc analysis? The measurement should be taken at the ICMR input range and NOT at 0v input?

I also did an ac simulation. In my setup, the input transistor M4 and M5 are biased at the center of ICMR 1.e. ~1.55V and input VAC=1V. Is this correct? I don't think that i need to bias the input transistors at 0V??

Notice from my simulation, output voltage (which is same as VDM4 in the graph) has an offset. Ideally it was supposed to be zero (quescient point) but simulation shows about ~400mV. Is this a common mode offset voltage? Is it difference from input offset voltage Vos? How to relate/calculate this common mode offset and how to reduce?

cheers
sj

 

[keith1200rs]

You can see the waveform from the attachment. From the graph, ICMR is 1.4V - 1.7V. Is this correct?

sj

It doesn't seem right. That configuration should go close to the positive rail and within maybe 1V to 1.5V of the negative rail. You don't seem to be sweeping VSWEEP to -5V (unless you just haven't shown that).

I am not sure if some of the confusion has arisen due to the fact you are working with split rails. For example, you are looking for when MN3 goes ohmic i.e. when VDS < VGS - VT. I would expect this to be maybe 1V depending on transistor sizing and process (e.g. running at a VGS of 2V with a 1V threshold). So that is 1V above the negative rail or -4V. You show it at -2V which seems very high.

I am confused by whether you are plotting absolute or relative voltages on your graphs. VGM4-Vth for example is a relative voltage with a fixed value subtracted from it. Is your plot of VDM4 a plot of the absolute value of VD or actually a relative voltage VDS (which is what is required for looking for when MN4 goes ohmic).

Sorry, not much help, but your results don't seem right - even though the transistor sizes are strange for a practical amplifier, I would still expect a larger common mode range.

Keith

 

[sjamil02]

Keith,

Thanks for your reply.

In my simulation i swept the dc voltage from -5V to 5V. See attachment.

I am not sure if some of the confusion has arisen due to the fact you are working with split rails. For example, you are looking for when MN3 goes ohmic i.e. when VDS < VGS - VT. I would expect this to be maybe 1V depending on transistor sizing and process (e.g. running at a VGS of 2V with a 1V threshold). So that is 1V above the negative rail or -4V. You show it at -2V which seems very high.

In the current reference branch, transistor's size MP1 and MN2 are the same. So the voltage across Source-Drain or Source-Gate of MP1 is ~ 6.3V and Gate-source or Drain-Source of MN2 is ~ 3.7V (This makes sense since Weff1/Leff1=Weff2/Leff2 and Un IS NOT equal to Up). So the VDS_sat of MN3(tail transistor) = 3.7-Vt = 3V OR VD_sat of MN3 = -2V (with respect to GND as we can see from the graph).

I am confused by whether you are plotting absolute or relative voltages on your graphs. VGM4-Vth for example is a relative voltage with a fixed value subtracted from it. Is your plot of VDM4 a plot of the absolute value of VD or actually a relative voltage VDS (which is what is required for looking for when MN4 goes ohmic).

VDM4 is the obsolute drain voltage with respect to GND. Similar with gate voltage VGM4. By the way, Vt of M4 is higher due to body effect (M4 bulk is tied to -VSS).

cheers

 

[sjamil02]

I don't think joining the inverting & non-inverting inputs of an opamp is the correct way to determine common mode range. I would suggest trying to connect it as a simple buffer and sweeping the non-inverting input.

I tried your suggestion. Tied inverting input to output and sweep non-inverting input. Here's the graph. How to explain ICMR from the graph?

Even so, that wouldn't isolate input range from output range.

Can you elaborate more.

Cheers
sj

 

[keith1200rs]

OK, I didn't realise you had such a large current through such small transistors (w/l), in which case your very narrow common mode range is plausible. I assume this is purely an exercise and isn't meant to be a practical circuit?

Referring to your other question about the gain, you must fix the common mode voltage within your valid range to measure the usable gain - so between 1.4V and 1.7V in your case, no 0V. I would expect the gain to be maybe 20, not 0.2 as you have measured. However, is it the common mode rejection ratio you want (which is the inverse of the common mode gain) or differential gain? For differential gain you need to fix one of the inputs at a DC voltage within your common mode range and apply an AC voltage source from that voltage to the other input.

You should get the same gain from an AC or DC analysis.

Make sure you probe MN5 drain, not MN4 when measuring the gain.

Keith.

Added after 3 minutes:

I don't think joining the inverting & non-inverting inputs of an opamp is the correct way to determine common mode range. I would suggest trying to connect it as a simple buffer and sweeping the non-inverting input.

I tried your suggestion. Tied inverting input to output and sweep non-inverting input. Here's the graph. How to explain ICMR from the graph?

Even so, that wouldn't isolate input range from output range.

Can you elaborate more.

Cheers
sj

Ignore that - I think it will only serve to confuse matters.

Keith.

 

[sjamil02]

Yes. The circuit only serves as an exercise and not for any practical purpose.

I would expect the gain to be maybe 20, not 0.2 as you have measured

The common mode gain Avcm obtained from dc sweep (measure output voltage gradient within common mode input range) is very small (0.02). The same for the gain obtained in ac analysis, with the same input bias condition which around Avcm=-31dB as you can see from the graph.

I concluded the simulation technique is correct. Please advice if you feel otherwise

Thanks for your help.

 

[keith1200rs]

Yes. The circuit only serves as an exercise and not for any practical purpose.

I would expect the gain to be maybe 20, not 0.2 as you have measured

The common mode gain Avcm obtained from dc sweep (measure output voltage gradient within common mode input range) is very small (0.02). The same for the gain obtained in ac analysis, with the same input bias condition which around Avcm=-31dB as you can see from the graph.

I concluded the simulation technique is correct. Please advice if you feel otherwise

Thanks for your help.

If it is common mode "gain" that you are interested in then -31dB is probably a realistic value although it would normally be expressed as a common mode rejection ratio (CMRR) of 31dB, not a "gain".

Keith.