Aoxomox
Member level 5
Hi all,
I am designing a DSP board with ADSP-21161N. My idea was connecting 8ns SRAM to the external data port. The input clock should be 50MHz and the core frequency will be generated by PLL with factor x2 -> 100MHz. Then I had a look at the timing requirements of the DSP an found that for my configuration there is a maximum 5.5ns time for "adress select delay to data valid" tDAD and only 3.25ns for "/RD low to data valid". The second time is possible with my chip, but the first time is never possible. I don't understand why I have to find a (5ns) 200MHz SRAM for a 50MHz asynchron operation with the Sharc.
Can anyone help??
Thank you all,
aOxOmOx
I am designing a DSP board with ADSP-21161N. My idea was connecting 8ns SRAM to the external data port. The input clock should be 50MHz and the core frequency will be generated by PLL with factor x2 -> 100MHz. Then I had a look at the timing requirements of the DSP an found that for my configuration there is a maximum 5.5ns time for "adress select delay to data valid" tDAD and only 3.25ns for "/RD low to data valid". The second time is possible with my chip, but the first time is never possible. I don't understand why I have to find a (5ns) 200MHz SRAM for a 50MHz asynchron operation with the Sharc.
Can anyone help??
Thank you all,
aOxOmOx