ADE XL switch view list for simulating verilog functional code

[dirac16]

I have run into a problem with simulating a verilog code in ADE XL window. Here are what I have done so far:

1. Created a new cellview, cellA, and chose its cell type as Verilog and its cell view as functional under Library myLib.
2. By clicking OK a text editor popped up, then wrote down a simple verilog behavioral code right there.
3. Clicked OK and hopefully there was no compilation error.
4. It then asked me to create a symbol. Clicked OK and a symbol was created successfully.
5. Now created another cellview, cellB, and this time chose its cell type as schematic.
6. In the new cellview I placed the symbol I just created.
7. I connected input pins to appropriate signals before running a simulation.
8. I created an ADE XL environment within which a transient analysis was set up.
9. When I ran the simulation I got an error as such: Unable to descend into any of the views defined in view list, 'spectre cmos_sch coms.sch schematic veriloga', for the instance 'I0' in cell 'cellB'. Add one of these views to the cell 'cellA' in the library 'myLib', or modify the view list so that it contains an existing view.
10. I have no idea why it presumably chose veriloga in the view list while I had originally verilog code in my design. Anyway, I tried to change the view list and replaced veriloga with functional view. This time I got another error, saying that the instance 'I0' is referencing an undefined module or subsircuit.

It seems that there has to be something wrong with the view list. What is the correct setup for switch view list when trying to simulate a verilog code? Any help is appreciated.

 

[Dominik Przyborowski]

You cannot simulate Verilog code in analog simulator.
You have to set a proper mixed mode simulation.

 

[dirac16]

You cannot simulate Verilog code in analog simulator.
You have to set a proper mixed mode simulation.

Thanks for the hint. Would you please let me know how to set a mixed mode simulation then? I need to put together many analog, digital and also behavioral Verilog blocks and run mixed signal simulations.

 

[dpaul]

I need to put together many analog, digital and also behavioral Verilog blocks and run mixed signal simulations.
One possibility is to write a behavioral description of the analog block using Verilog HDL. Then that model in .v format can be used with your usual digital block. Now you can use any industry standard simulator used for simulating digital designs.

Note that I am talking about Verilog HDL and not Verilog AMS.

 

[dirac16]

Finally I could make AMS simulation up and running thanks to @dominik's great hint!

--- Updated Nov 25, 2021 ---

I need to put together many analog, digital and also behavioral Verilog blocks and run mixed signal simulations.
One possibility is to write a behavioral description of the analog block using Verilog HDL. Then that model in .v format can be used with your usual digital block. Now you can use any industry standard simulator used for simulating digital designs.

Note that I am talking about Verilog HDL and not Verilog AMS.

I was thinking on the opposite side actually! I wanted to model my digital blocks using VerilogA because ADE can hopefully handle all-analog blocks. But don't know if that is a good practice.

 

[dpaul]

@dirac16
You can try that also.
I told you that method because years ago, I had modelled an analog part using VHDL and had used it in further digital parts of the IC design.