skyglider
Junior Member level 1
We have included Analog Devices AD7725 ADC in our last design, but we cannot succed to make ADC running. 16 ADCs are connected with parallel bus and controlled by Xilinx Spartan2 FPGA. I/O bus is driven with 3.3 LVTTL IO as ADC specification allow signals (all digital except clock) to be driven with VCC lower than 5V. After power-up ADC interrupt is asserted, after that BFR and RdCONV instructions are issued to all converters and converters are synced using SYNC signal. The problem is that received data is not valid. Does anyone have any experience in using AD7725 in similar environment?
