Georgy.Moshkin
Full Member level 5
My question briefly:
New schematic is the same as combo-bias on this picture (most-right picture)
My Rs is around 40 Ohm
On this schematic, if current Ids becomes more negative with more negative Vgs (till some point), does not it lead to larger Igs which again result in more negative Vgs? As Vgs will depend on Igs and vice versa, would not it make impossible to achieve some biasing points, because biasing will be always tend to settle near maximum Igs?
My question details:
I just finished prototype testing of my new VCO. Now I want to remove negative voltage supply.
I use very simple biasing scheme, using single resistor Rdrain, Vcc=5v.
Drain pin: Single resistor Rdrain determines load curve, Rdrain is connected between drain pin and 5v supply. Voltage drop across Rdrain as around 1..1.5v
Source pin: source is connected to ground through high impedance biasing line
Gate pin: is biased at 0...-1v through high impedance biasing line.
Frequency of oscillation is determined by biasing: F=f(Vgs)
Now I want to connect Rdrain between ground and source pin, so Vg becomes negative relative to Vs without using negative voltage supply. Then applying 0..+1v biasing voltage to Vg will achieve the same effect as applying -1v..0v in initial setup. The problem is that voltage drop across resistor depends on Vgs voltage:
1) if I make Vgs more negative by some amount , current through FET is increased
2) as current is increased, voltage drop U=R*I is increased too, leading to even more negative Vgs:
In initial setup source pin was directly connected to ground and Vs did not depend on Vgs.
In new setup source voltage is lifted above the ground using resistor.
F=f( Vgs( I( Vgs(...) ) ) ). Will it settle at some biasing point, or such biasing scheme is a bad idea? Would not it self-bias itself to some point near -0.8v instead of biasing at say -0.2v, and also make bias oscillate around -0.8v with some low khz...mhz range frequency?
New schematic is the same as combo-bias on this picture (most-right picture)
My Rs is around 40 Ohm
On this schematic, if current Ids becomes more negative with more negative Vgs (till some point), does not it lead to larger Igs which again result in more negative Vgs? As Vgs will depend on Igs and vice versa, would not it make impossible to achieve some biasing points, because biasing will be always tend to settle near maximum Igs?
My question details:
I just finished prototype testing of my new VCO. Now I want to remove negative voltage supply.
I use very simple biasing scheme, using single resistor Rdrain, Vcc=5v.
Drain pin: Single resistor Rdrain determines load curve, Rdrain is connected between drain pin and 5v supply. Voltage drop across Rdrain as around 1..1.5v
Source pin: source is connected to ground through high impedance biasing line
Gate pin: is biased at 0...-1v through high impedance biasing line.
Frequency of oscillation is determined by biasing: F=f(Vgs)
Now I want to connect Rdrain between ground and source pin, so Vg becomes negative relative to Vs without using negative voltage supply. Then applying 0..+1v biasing voltage to Vg will achieve the same effect as applying -1v..0v in initial setup. The problem is that voltage drop across resistor depends on Vgs voltage:
1) if I make Vgs more negative by some amount , current through FET is increased
2) as current is increased, voltage drop U=R*I is increased too, leading to even more negative Vgs:
In initial setup source pin was directly connected to ground and Vs did not depend on Vgs.
In new setup source voltage is lifted above the ground using resistor.
F=f( Vgs( I( Vgs(...) ) ) ). Will it settle at some biasing point, or such biasing scheme is a bad idea? Would not it self-bias itself to some point near -0.8v instead of biasing at say -0.2v, and also make bias oscillate around -0.8v with some low khz...mhz range frequency?
Last edited: