Accounting for clock jitter in RTL (VHDL)

[Yasmine4]

Hello all,

I am expecting my clock to jitter by -5% or +5% in real life, and I have to take that in consideration while writing my RTL, because many values and cases depend on the period of my clock.

My question is: is there a common way to detect or account for clock jitter in RTL ? it doesn't seem very obvious to me given the fact that almost everything depend on the clock.

One idea that occurred to me is maybe creating a separate design sub-block to only take care of this detection. and feed the needed decision to the rest of the design.

Thanks and best regards
Yasmine

 

[shlooky]

Hi there,

While coding RTL (AKA frontend), you consider your clock to be ideal.
Your RTL simulation will work even with 100 GHz clock frequency, even if it is impossible in real life.

Non-idealities of clock signal are considered during backend - synthesis and PnR and sign-off checks.
Synthesis uses ideal clock tree, but accounts for clock jitter, latency, flip-flop timing requirements, etc. synthesis still uses ideal clock for hold checks since the clock tree is ideal.
Clock Tree Synthesis (CTS) during PnR builds a real clock tree accounting for all defined imperfections... these are also called "design/timing constraints" (look-up "SDC" file)

Hope this helps.

Shlooky

 

[ads-ee]

I am expecting my clock to jitter by -5% or +5% in real life, and I have to take that in consideration while writing my RTL, because many values and cases depend on the period of my clock.

What is generating such a clock? Oscillators are usually are spec'd with jitter in PPM (Parts Per Million) a typical oscillator will be 100 PPM, which isn't anywhere near +/- 5%.

As @shlooky stated you would normally handle the jitter in your SDC file.

 

[ThisIsNotSam]

Hello all,

I am expecting my clock to jitter by -5% or +5% in real life, and I have to take that in consideration while writing my RTL, because many values and cases depend on the period of my clock.

My question is: is there a common way to detect or account for clock jitter in RTL ? it doesn't seem very obvious to me given the fact that almost everything depend on the clock.

One idea that occurred to me is maybe creating a separate design sub-block to only take care of this detection. and feed the needed decision to the rest of the design.

Thanks and best regards
Yasmine

You need some textbook knowledge of digital systems. And basic reasoning. How can you measure the drift of a clock while using the clock itself as reference?

 

[shlooky]

What is generating such a clock? Oscillators are usually are spec'd with jitter in PPM (Parts Per Million) a typical oscillator will be 100 PPM, which isn't anywhere near +/- 5%.

As @shlooky stated you would normally handle the jitter in your SDC file.

Hi,

if you design the oscillator yourself, you can set the ratio between required silicon area and "tightness" (standard deviation) of your parameters using Monte-Carlo simulations...

Precision ads-ee mentiones is probably achieved by trimming and/or additional calibration circuits.

Shlooky