[SOLVED] Accessing an instance from different modules in Verilog

[yassendobrev]

Hi all,

I am trying to make a single instance of a module accessible in different modules without instantiating it in every module.

In my case I have a ROM containing some data, generated before syntheses, which should be accessible from different modules in my design. If I instantiate it in each module, than there are two copies of it, taking up twice as much Block RAM as needed.

There is no concern about modules trying to access it in the same time, as they run one after the other.

Thanks in advance for any help!

 

[shitansh]

Hi,

In this case you need to handle read_enable, write_enable, read_data, write_data, read_address and write_address from different module and need to pass this control and data signals to one module.

You can not instantiate two copy of same, synthesis tool will made two different ramblocks.

HTH
Shitansh Vaghela

 

[mux_master]

You will probably want to use a dual port ROM so that both modules can access it at the same time.

 

[yassendobrev]

I am using a multiple-port ROM and my current idea is to access it from the top module via the 2nd module. This means, that I'll have to add some additional inputs and outputs to the 2nd module for simple ROM access (similar to a "transparent property").

I don't like it, but I don't see any alternative