IWe Ivan Govnov
Newbie level 6
Hello!
I have multiple LIS2DS12 accelerometers; according datasheet, it is possible to get
data rate high as 3200 and even 6400 Hz. In both cases there are built-in filter with
1420 or 2840 Hz cutt-off frequency. As this accelerometer have internal multiplexer, I
can expect a sampling frequency ODR*3 for each channel (X,Y,Z). In all cases build-in
filter reject all signal components in range higher then F(sampling)/2.
But, it is way to increase accelerometer bandwidth by using, for example, more then
one. In this case they should start with delay.
τ=(n-1)*T/(M+1),where T - sampling period, n - number of sampling device, M - total number of sampling devices.
It is look like easy to implement using timer of MCU, especially when accelerometer work in FIFO mode.
The frequencies seems to be is not so high to worry about jitters, delays and other stuff. The
expected bandwidth should be near ODR*N (N - number of used devices) but LPF of each
accelerometers should place constrains on bandwidth too.
But:
1) in my board accelerometers placed rather compact but not in same point. What can I
do to solve it?
2) I have a "blind" point at frequency near ODR. For example, if final F(s) should be
12800 Hz for 4 accelerometer, the signal of frequency near 3000...3400 Hz is rejected.
It is possible to recover it?
3) Output signal seems to be so noisy, but this may be a consequence of point 1
(placing of accelerometers) which leads to variety of gain.
4) FFT of measured signal seems to have parasitic bins in zone between 3200 to 6400 Hz
for F(sampling)=12800 Hz.
What further steps should I do?
I have multiple LIS2DS12 accelerometers; according datasheet, it is possible to get
data rate high as 3200 and even 6400 Hz. In both cases there are built-in filter with
1420 or 2840 Hz cutt-off frequency. As this accelerometer have internal multiplexer, I
can expect a sampling frequency ODR*3 for each channel (X,Y,Z). In all cases build-in
filter reject all signal components in range higher then F(sampling)/2.
But, it is way to increase accelerometer bandwidth by using, for example, more then
one. In this case they should start with delay.
τ=(n-1)*T/(M+1),where T - sampling period, n - number of sampling device, M - total number of sampling devices.
It is look like easy to implement using timer of MCU, especially when accelerometer work in FIFO mode.
The frequencies seems to be is not so high to worry about jitters, delays and other stuff. The
expected bandwidth should be near ODR*N (N - number of used devices) but LPF of each
accelerometers should place constrains on bandwidth too.
But:
1) in my board accelerometers placed rather compact but not in same point. What can I
do to solve it?
2) I have a "blind" point at frequency near ODR. For example, if final F(s) should be
12800 Hz for 4 accelerometer, the signal of frequency near 3000...3400 Hz is rejected.
It is possible to recover it?
3) Output signal seems to be so noisy, but this may be a consequence of point 1
(placing of accelerometers) which leads to variety of gain.
4) FFT of measured signal seems to have parasitic bins in zone between 3200 to 6400 Hz
for F(sampling)=12800 Hz.
What further steps should I do?