Danielye
Junior Member level 3
How to implement the time-tagging
circuit and firmware, which has a gain of Kdet = 1bit/ns.
This phase detector with 1ns resolution is for the DPLL, including the digital loop filter.
Could someone kindly provide some materals about the time tagging circuit?
Thanks in advance!
circuit and firmware, which has a gain of Kdet = 1bit/ns.
This phase detector with 1ns resolution is for the DPLL, including the digital loop filter.
Could someone kindly provide some materals about the time tagging circuit?
Thanks in advance!