about the rtl view in xilinx

[kannan2590]

actually in my project i have included the components for lsfr(data generator),iq mapper,polyphase and clock generator.
IN the RTL view the components of clock generator,lsfr,iq mapper are visible but the only component Polyphase is not at all visible. where is the mistake or problem is it the problem of the code 'if it is the problem of code then give the idea of solving the problem.the upsampling factor used is 32 and if it is some other problem please inform me.

 

[h@ro]

Although I use Altera software, modules will not be visible in the RTL viewer if they do not synthesise properly, so in this case I'd suggest there is an issue with your code. Check warnings to see if inputs to 'Polyphase' drive logic or not. Better yet, simulate the modules together.