About the p-channel input stage? (question about martin's)

[Markie]

hi, guys:
I am confused about the chapter 5 "Basic Opamp Design and compensation" of Martin's. he says that "SR=Veff1*wta". I think that SR is the large signal parameter, Veff1 and wta is small signal paramter, Can they soluted like that? Maybe Ic/Cc is the perfect one. (wta means unit gain bandwidth)

In page 231 "n-Channel or p-Channel Input Stage" section, it says "For a given power dissipation, and therefore bias current, having a p-channel input pair stage maximizes the slew rate. This result is seen from SR=Veff1*wta, since p-channel input transistors for the first stage have a large Veff than would be the case for n-channel input transistors(assumig similar maximum widths have been chosen to maximize the gain). ------yes, the Veff is larger, but can it sees the wta ? or it assumes that wta is constance? GB=gm1/Cc, no, I don't think so.

another question is : if used in SC circuit, they say that considered the speed, we should decrease the input parasite capacitor. Do you still use the p-channel as input stage?

thanks a lot for every answer.

 

[terryssw]

Re: About the p-channel input stage? (question about martin'

For the parameters wta, I don't quite understand what's the meaning is.

For your last questions, The input parasitic cap will degrade your feedback factor in SC circuits during the amplify phase, and thus reducing your speed. For the same power budget using nmos input pair will have higher transconductance and equivalently smaller input capacitors, thus high-speed opamps usually use nmos input pair. However, in some opamp configuration using pmos input stage may maximize slew rate, so this is the trade-off rule in analog world.... No opamp will satisfy all application requirement (if it really can, why we have so many types?)

 

[Markie]

Re: About the p-channel input stage? (question about martin'

thank for your answer, wta means the unit gain bandwidth.

Can you give me some more advices for the last question?

 

[borodenkov]

another reason of using PMOS as input is to minimize flicker-noise (NMOS is noisier than PMOS), but as written earlier, it will increase power consumption since gm/Id ratio is worth for PMOS

 

[gevy]

Re: About the p-channel input stage? (question about martin'

Martin is right.
The equation SR=I/C can enter you into error, that increasing a current or reducing the capasitor you will increase slew rate.
Actually increase of a current will cause proportional increase of the capasitor for maintenance of stability. The reduction of the capasitor is similar will cause proportional reduction of a current for maintenance of stability.
Thus equation enters you in error, as the parameters I and C depend from each other.
The equation SR=Veff1 Wta includes independent parameters and gives a real way of increase of SR.

 

[gevy]

Re: About the p-channel input stage? (question about martin'

Martin is right.
The equation SR=I/C can enter you into error, that increasing a current or reducing the capasitor you will increase slew rate.
Actually increase of a current will cause proportional increase of the capasitor for maintenance of stability. The reduction of the capasitor is similar will cause proportional reduction of a current for maintenance of stability.
Thus equation enters you in error, as the parameters I and C depend from each other.
The equation SR=Veff1 Wta includes independent parameters and gives a real way of increase of SR.

 

[terryssw]

Re: About the p-channel input stage? (question about martin'

If you want speed, then probably nmos input pair. But others parameters (such as flicker noise) will worse than pmos counterpart, you must determine which specifications is most important for you.

 

[Markie]

Re: About the p-channel input stage? (question about martin'

Martin is right.
The equation SR=I/C can enter you into error, that increasing a current or reducing the capasitor you will increase slew rate.
Actually increase of a current will cause proportional increase of the capasitor for maintenance of stability. The reduction of the capasitor is similar will cause proportional reduction of a current for maintenance of stability.
Thus equation enters you in error, as the parameters I and C depend from each other.
The equation SR=Veff1 Wta includes independent parameters and gives a real way of increase of SR.

Can you give me a detail explain about increasing SR methods?

I still think it confused large signal params with small signal params!

 

[gevy]

Re: About the p-channel input stage? (question about martin'

The parameters of a small and large signal are not completely independent, as they describe the same transistor.
For increase of SR it is necessary to increase a current and to reduce capacitor (SR=I/C), but to keep stability (phase margin). The problem is, that increase of a current and the reduction of capacitor results in decrease of stability (the phase margin decreases)!
In this case increase of a Veff1 at the same transconductance is increase of a current, and the increase of Wta results in increase of phase margin, that is capacitor can be less.
The summary.
The increase of a Veff1 and Wta is a way of increase of a current and reduction of capacitor at constant stability. It is a way of increase of SR.

 

[Markie]

Re: About the p-channel input stage? (question about martin'

another reason of using PMOS as input is to minimize flicker-noise (NMOS is noisier than PMOS), but as written earlier, it will increase power consumption since gm/Id ratio is worth for PMOS

Sorry for disturbing you!

You say that because gm/Id ratio is worth for PMOS, the circuit will increase power consumption.

Due to my knowledge, gm/Id only relates to the over-voltage!

Can you explain it clearly?

thanks

 

[fehler]

Re: About the p-channel input stage? (question about martin'

another reason of using PMOS as input is to minimize flicker-noise (NMOS is noisier than PMOS), but as written earlier, it will increase power consumption since gm/Id ratio is worth for PMOS

Sorry for disturbing you!

You say that because gm/Id ratio is worth for PMOS, the circuit will increase power consumption.

Due to my knowledge, gm/Id only relates to the over-voltage!

Can you explain it clearly?

thanks

I am with Markie that the gm/Id only relates to the over-drive voltage. The only
disadvantage for P mos input stage is that the gate area should be larger, which
induce large input cap.

 

[fehler]

Re: About the p-channel input stage? (question about martin'

hi, guys:
I am confused about the chapter 5 "Basic Opamp Design and compensation" of Martin's. he says that "SR=Veff1*wta". I think that SR is the large signal parameter, Veff1 and wta is small signal paramter, Can they soluted like that? Maybe Ic/Cc is the perfect one. (wta means unit gain bandwidth)

In page 231 "n-Channel or p-Channel Input Stage" section, it says "For a given power dissipation, and therefore bias current, having a p-channel input pair stage maximizes the slew rate. This result is seen from SR=Veff1*wta, since p-channel input transistors for the first stage have a large Veff than would be the case for n-channel input transistors(assumig similar maximum widths have been chosen to maximize the gain). ------yes, the Veff is larger, but can it sees the wta ? or it assumes that wta is constance? GB=gm1/Cc, no, I don't think so.

another question is : if used in SC circuit, they say that considered the speed, we should decrease the input parasite capacitor. Do you still use the p-channel as input stage?

thanks a lot for every answer.

1. I think that the equation SR=Veff1*wta implies that, for a given input stage
Veff, if you need larger wta, then you must increase the current, then the SR.
Just so so. But what will happen if you maitain the current Iss? then
Veff1 * wta = Veff1 * gm1 / Cc = Veff1 * Iss / Veff1 / Cc = Iss / Cc. Then SR
will never change. So, if Iss is small, even a large Veff1 helps nothing on SR
improving.

2. I dont think that P pair could give larger SR, as you discussed before.