About String Matching

[hei1233212000]

Hi, I am a newcomer.

Now I am doing a String Matching Machine (test the string "ABC" or "abc"). When I finish a draft and I want to simulate it. But, the state flow is out of my expectation, there is an undefined state. See Fig1.

What is the problem?

Furthermore, when I simulate the waveform (Quartus II 7.2), two warnings occur:

Warning: Wrong node type and/or width for node "|Test01|state" in vector source file. Node in design is of type Enum and of width 1, but node in vector source file is of type 9-level and of width 1.

Warning: Signal name "|Test01|state" changed to enum type

What do they mean?

And,

Last but not least, can someone teach me how to display the internal signal (state ) using Xilinx ISE?
I have found a topic here but I still cannot drag the internal signals into the waveform.


I appreciate your help.

My code:

Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use std.textio.all;

Entity Test01 is
	Port(  clk			: in  std_logic;
		 reset		: in  std_logic;
                 string_in           : in character;
		 ABC	  		: out std_logic);
End Test01;

Architecture a of Test01 is

	 type state_type is (idle, ss, s0, s1, s2, s3);
	 signal state, next_state        :state_type;

Begin 
     change_state: Process(reset, clk)
     Begin
          if reset = '1' then                             --reset system     
                 state <= idle;

          elsif (rising_edge(clk))  then
                     state <= next_state;                 --update state on clock
					 if (state = s3)  then 
                          ABC <= '1';            
					 else
                          ABC <= '0';            
					 end if;
                
          end if;
     end process change_state;

     process_bit: Process(state, string_in)
     Begin        
                case state is
                             when idle => 
						next_state <= ss;
                             when ss => 
                                                next_state <= s0;
                             when s0 =>	
					 if (string_in='A') or (string_in='a')then  
						next_state <= s1;
					 else 
						next_state <= ss;
					end if;
                             when s1 =>
					 if (string_in='B') or (string_in='b')then
						next_state <= s2;
					 else 
						next_state <= ss;
					 end if;
                             when s2 =>
                                         if (string_in='C') or (string_in='c') then
                                                next_state <= s3;
					 else 
						next_state <= ss;
					 end if;
                             when s3 =>
					next_state <= s3;
                 end case;
      END process process_bit;
End a;

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