Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

About S*y*n*p*l*ify ASIC and DC ?

Status
Not open for further replies.

GoodMan

Full Member level 2
Joined
Sep 30, 2002
Messages
125
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,298
Activity points
646
hi all,

In DC , can use a script file to run worst case(setup time)and to run
best case (hold time).
but in sy*n*p*l*i*fy ASIC how to use a prj to run worst and best case?
(first run worst case,then use worst case output file to run best case)


have a nice day! :oops:
 

you can build the environment before you synthesis
 

you can build the synthesis constraints configuration for your design objects before synthsising. The best or worst case are only the valid when configurating timing constraints.
 

you can set the max and min libraries in the .synopsys file!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top