about PLX PEX8311 - low local bus efficiency

[leonqin]

pex8311 + fpga

a pciexpress->Localbus Bridge

low local bus efficiency I got.

why?

when transfer data beteween pex8311 and local device(fpga),I sent ready signal to pex8311 ,but pex8311 abort the transfer after transfer about 100 words,and wait for times the time,it will transfer continue for 100 words ,and wait,,,, and so on.

 

[George111]

pex8311 local bus bridge

Hi,

I have same problem.

Have You any result ?

George

 

[alfer1]

Is any body know: I Direct Master mode, if ADS# assert low for the whole access time (instead of one LCLK),just us a CPU's chip select CS# line connect with it,what will happen?
can data phase be valid,or still remain in address phase?

 

[zootjeff]

Re: pex8311 + fpga

a pciexpress->Localbus Bridge

low local bus efficiency I got.

why?

when transfer data beteween pex8311 and local device(fpga),I sent ready signal to pex8311 ,but pex8311 abort the transfer after transfer about 100 words,and wait for times the time,it will transfer continue for 100 words ,and wait,,,, and so on.

Was this on a read or a write? make sure prefetch is setup right.