stocking
Member level 5
libpli.so
Hi ,
Who can tell me how to load the PLI library into ncveril0g simulator?
I can't load into the PLI library for simulaiton using NCVERIOG simulator. Please go through the simulation warning information(in red) and ncverilog script(in pink).
please help me debug the issue and check whether the +loadpli option is writtern correctly. Thanks!
ncelab: *W,CUVWSI (../scr/AtlasV_Final_ver_02_07.v,1641489|20): 2 input ports were not connected:
ncelab: (/projects/pegasus/DK/LDO/IP_LDO_rel_V001/verilog/reg6003ka.v,9): AVDD33A
ncelab: (/projects/pegasus/DK/LDO/IP_LDO_rel_V001/verilog/reg6003ka.v,9): AVSS33A
$STILDPV_setup(
|
ncelab: *W,MISSYST (../scr/palm5_top_jtag_buf_stil_tb.v,361|16): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
If item was defined in a shared-object library, the problem could be:
libvpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library.
libpli.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library..
while ( !$STILDPV_done()) #($STILDPV_run());
|
ncelab: *W,MISSYST (../scr/palm5_top_jtag_buf_stil_tb.v,365|24): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
while ( !$STILDPV_done()) #($STILDPV_run());
ncverilog \
+nc64bit \
+licq_all \
+ncaccess+rwc \
+define+functional_mode \
+define+no_msg_ckg \
+notimingcheck \
+nctimescale+1ns/1ps \
-l ./../log/ncverilog.log \
#+loadpli1=debpli:novas_pli_boot \
#+loadpli1=libpli.so:/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI \
#+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so \
#+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so:STILDPV_done,STILDPV_run \
+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so:STILDPV_done,STILDPV_run \
+tcl+dump.tcl \
#tb_palm5_top.v \
#/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/palm5_top_jtag_buf_stil_tb.stil \
/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/AtlasV_Final_ver_02_07.v \
/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/palm5_top_jtag_buf_stil_tb.v \
Note: libpli.so is the PLI library name and the library directory is /nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI
STILDPV_done and STILDPV_run should be the defined function/task in the PLI library named libpli.so.
Hi ,
Who can tell me how to load the PLI library into ncveril0g simulator?
I can't load into the PLI library for simulaiton using NCVERIOG simulator. Please go through the simulation warning information(in red) and ncverilog script(in pink).
please help me debug the issue and check whether the +loadpli option is writtern correctly. Thanks!
ncelab: *W,CUVWSI (../scr/AtlasV_Final_ver_02_07.v,1641489|20): 2 input ports were not connected:
ncelab: (/projects/pegasus/DK/LDO/IP_LDO_rel_V001/verilog/reg6003ka.v,9): AVDD33A
ncelab: (/projects/pegasus/DK/LDO/IP_LDO_rel_V001/verilog/reg6003ka.v,9): AVSS33A
$STILDPV_setup(
|
ncelab: *W,MISSYST (../scr/palm5_top_jtag_buf_stil_tb.v,361|16): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
If item was defined in a shared-object library, the problem could be:
libvpi.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library.
libpli.so: cannot open shared object file: No such file or directory or file is not valid ELFCLASS64 library..
while ( !$STILDPV_done()) #($STILDPV_run());
|
ncelab: *W,MISSYST (../scr/palm5_top_jtag_buf_stil_tb.v,365|24): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
while ( !$STILDPV_done()) #($STILDPV_run());
ncverilog \
+nc64bit \
+licq_all \
+ncaccess+rwc \
+define+functional_mode \
+define+no_msg_ckg \
+notimingcheck \
+nctimescale+1ns/1ps \
-l ./../log/ncverilog.log \
#+loadpli1=debpli:novas_pli_boot \
#+loadpli1=libpli.so:/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI \
#+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so \
#+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so:STILDPV_done,STILDPV_run \
+loadpli1=/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI/libpli.so:STILDPV_done,STILDPV_run \
+tcl+dump.tcl \
#tb_palm5_top.v \
#/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/palm5_top_jtag_buf_stil_tb.stil \
/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/AtlasV_Final_ver_02_07.v \
/nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/palm5_top_jtag_buf_stil_tb.v \
Note: libpli.so is the PLI library name and the library directory is /nethome/zjwang/work/pegasus/from_samsung/A4_check/jtag_sim/A4/scr/0712SP4PLI
STILDPV_done and STILDPV_run should be the defined function/task in the PLI library named libpli.so.