About how to tune DPLL on receiver side.

[EDA_hg81]

In the system, there is a transmitter and a receiver.
I want to use the fixed pattern data generated at transmitter to tune the DPLL on receiver.
How can I realize this?
Thanks.:roll:

 

[sameh_yassin99]

Hello,
The synchronization problem may have two jobs between Tx. and Rx. There is bit synchronization, then frame synchronization.
Bit synchronization: tries to center the positive or negative edge of the clock at the center of the bit width. This is done through PLL.
Frame synchronizatiobn: such as in E1 frame which consists of 16 bits. At Transmitter,You can send a 32-bit synchronization pattern. The pattern is inserted at the start of each frame by sending single sync bit after 15 bits of data.
At the receiver, store 32 frames in along shift register (16bit*32). Finally make a simple decode circuit that takes the bits number 0,31,63,...,511 and compares them with your sync pattern.

I hope I touched ur question because it is not so clear what u exactly need.

regards,
S. Yassin

 

[EDA_hg81]

Thank you for your answer.

I have another question.

On the receiver side, the clock recovery PLL is tuned by incoming data.

But if those incoimg data are missing if the clock recovery PLL will be out of lock.

 

[sameh_yassin99]

Hello,
To extract clock from incoming data signal. Just as example, please read the following part datasheet T7296. It works as transmitter and receiver on the same chip.
Data is transmitted as differntial signal only (AMI pulses) without clock, while as a receiver it takes the differential signal as input and generates zeros and ones (HDB3 coded) with relative to locally generated clock.

Again, it just an example on how to extract clock from incoming signal. If you provide more details about your bit rate and frame shape, we can find a similar analog IC for it. Then, we can try to implement most of its function in VHDL and leaving the line interface functions to an external IC.

regards,
S. Yassin