bailibl
Newbie level 5
I need a delay circuit in my design.And i know some methods,for example,registers,counter,buffer and cascade inverter.
But it 's not permitted to use registers and counter in my design.
therefore i could use buffer and cascade inverter.
i encountered a problem when i used buffer and cascade inverter that either buffer or cascade inverter was removed by synthesis tools.
By the way,i have turned off all exiting option settings in Analysis & Synthesis settings in QUARTUS II 4.2.
Is there anyone who have encountered this problem like this?
Please tell me how could i solve this problem?
Reply my topic or mail me :bailibl@126.com
But it 's not permitted to use registers and counter in my design.
therefore i could use buffer and cascade inverter.
i encountered a problem when i used buffer and cascade inverter that either buffer or cascade inverter was removed by synthesis tools.
By the way,i have turned off all exiting option settings in Analysis & Synthesis settings in QUARTUS II 4.2.
Is there anyone who have encountered this problem like this?
Please tell me how could i solve this problem?
Reply my topic or mail me :bailibl@126.com
