A problem in post-simulation

[gonewithstone]

I meet a problem when run post-simulation. In the netlist, the cell port RXADCLK is connect to signal \uSub/uIo/uSerdesRx0/RXADCLK, as below shown:
HSR \uSub/uIo/uSerdesRx0/HC (
.RXADCLK(\uSub/uIo/uSerdesRx0/RXADCLK ),
...................
)
However, according to the post-simulation waveform, there's 2.2ns delay between RXADCLK and \uSub/uIo/uSerdesRx0/RXADCLK. In sdf file, there's no constrains for RXADCLK and \uSub/uIo/uSerdesRx0/RXADCLK. I think the RXADCLK and \uSub/uIo/uSerdesRx0/RXADCLK should change simultaneous due to the direct connect relation, So I cann't find the reason to explain the 2.2ns timing delay. Anyone can help me?

 

[sachin_kirdat]

can you attach part of ur sdf file for this cell and interconnect portion.

this delay is for inter connection (routing delay). In ur SDF file search for the this signal hieracy you will get it.

 

[gonewithstone]

Thanks for your reply! I have find the reason when I try to fix the SDF warning in compile.log. I' m a newer to do post-simulation, I think it's important to focus on SDF warning infomation in simulation when debug.