a high resolution low offset comparator

[extraord]

hi folks,
recently I'm designing a circuit which need a very accurate comparator.
the resolution must be smaller than 1mv.
also the offset has to be less than 2-3mv(3 sigma).
the process is tsmc13 logic. the area of it should be within 30umx30um
speed is not very critical, 30ns for settling is ok.
is that possible? how about if the offset can be 5mv(3 sigma)?
what should i concern more about? input pair size? layout?

is there anybody who has taped it out with the similar spec?

how about the really testing result?
thanks a lot

 

[kumard35b]

I have worked with the comparator for 0.25um technology and also had the spec of
2mv offset luckily one sigma..
for this design i used large area device w=80um and l=2um ....
and the next stage is my cascode stage ...followed by two differential stage and the conversion from differential to single ended,i have used a mos diode with current mirror and output stage (3 inverters ) to drive 1pf load.

I think for your design if current is not a constraint then you can start with 5uA as bias current and start the design with input transistors as some 80/4.

the offset formula is delta VT = Av/sqrt(W * L)

from model file you can find the Av value of your mos device then start the design with the ratio

 

[extraord]

thanks for your help.
I know the Av=3mV*1u.
one more thing I want to know is how much difference of
offset between your estimation and test results?
or your simulation in monte carlo and test results.

 

[mark_nctu]

VT = Av/sqrt(W * L) x3 ==> 3 sigma

I have worked with the comparator for 0.25um technology and also had the spec of
2mv offset luckily one sigma..
for this design i used large area device w=80um and l=2um ....
and the next stage is my cascode stage ...followed by two differential stage and the conversion from differential to single ended,i have used a mos diode with current mirror and output stage (3 inverters ) to drive 1pf load.

I think for your design if current is not a constraint then you can start with 5uA as bias current and start the design with input transistors as some 80/4.

the offset formula is delta VT = Av/sqrt(W * L)

from model file you can find the Av value of your mos device then start the design with the ratio