A general Clocking circuit question

[skywalkerluk]

Hello everyone,

I am trying to design a circuit and using a NMOS transistor as a clocked switch. The gate of the NMOS is connected to a periodic clock signal going from 0 to Vdd. This will make the drain current change periodically with the gate-to-source voltage (Vgs) and may affect other components in the circuit significantly (like distorting waveforms). Are there any solutions around this?

Thank you very much.

 

[crutschow]

Can't help you much unless you post the circuit. ;-)

 

[skywalkerluk]

Hi crutschow,
Thanks for your reply!

I am trying to build a latched comparator circuit with a pre-amplifier for a flash ADC (please refer to my attached labeled cadence schematic and simulated waveforms).

I applied input signal as shown in the waveform plot (top two), at V_in+ and v_in-. The differential input signals are completely normal. I took the simulated waveform at V_out+ and V_out-, and got the two (differential) plots as shown in the waveform plot (bottom two), and get distorted waveforms. The correct waveform should look the same as the input, except differentially amplified...

From some analysis, I could see the reason for the distortion:
Transistors A1&A2 (fed by the periodic clock pulse at the gate) has varying V_gs, and according to MOS characteristic equation, I_d changes with V_gs. The change of I_d in turn affects the V_gs of the transistors B1&B2, which represent the same node as V_out+ and V_out-, interfering with the originally amplified signal.

If I disconnect the pre-amplifier with the comparator, the pre-amplifier amplifies the input signals beautifully and differnetially. (The comparator works fine when disconnected with the pre-amplifier as well.) The distortion problem only happens when I connect the pre-amplifier with the comparator, and it is apparently affected by the clock signal.

Are there any ways to get around this problem and make the whole latched comparator (with the pre-amp) work?

Thanks in advance!!