A basic question on Verilog simulation

[eruisi]

In IEEE standard 1364, it says the following code

module test;
wire p;
reg q;
 
assign p = q;
initial begin
        q = 1;
        #1 q = 0;
        $display("At time: %t, the value is %f\n", $realtime, p);
end
endmodule

could either display p as a "1" or "0". I can't understand why.
#1 q = 0 is a blocking assignment, the display should be executed after #1 q=0 is finished at time 1, right? I run the simulation in vcs and got 0 but in ncverilog got 1.

Could you tell me how this happens.

Thanks a lot!

 

[semiconductorman]

yes , " #1 q = 0; " is a blocking statement. But the value being printed out is p not q so here is the deal , when you do "assign p=q" it spons out as a spearate thread, or in verilog terms it is equivalent to writing always@ (q) p=q; Right ? When you do this , the print statement may be executed delta cycle before q is assigned to p or after q is assinged to p. That's why it is not predictable but if you do put a delay before print than this will work fine and always print the value of p after q is assigned to it. other way around if you put a delay in assigning q to p , print will always print value of p before q is assigned to it.