myle00
Newbie level 5
Hi,
I'm trying to connect multiple 74hc595 shift register in series so that I can get more than 8 bits output. The problem is that the data output of the first shift register, which is supposed to be the data input to the second sr, is early by half of a clock cycle relative to the input data. The attached scope picture shows what I mean. The yellow (ch1) line is the clock signal that I generate. The blue line (ch2) is the data that I send to the first 74hc595. The green line (ch4) is the data output that I'm supposed to use as the input for the next shift register. However, because it's early by a half cycle relative to the clock, the data output on the second shift register is wrong.
To be more precise, the output (ch4) data line, is supposed to delay the input data line (ch2) by 8 clock cycles, but from the image you can see it's delayed by only 7.5 cycles, which brings that out of sync.
The device that outputs these signals to the shift register is either an FT232 or an FT2232H (used for the picture attached), both in bit bang mode. It's weird because from my identical boards using this shift register, some have this problem while others don't. I suppose the issue is because of some impedance mismatch, but I don't know how to solve it. I do place filtering capacitors (0.1uF) at VCC.
Thanks,
Matt
I'm trying to connect multiple 74hc595 shift register in series so that I can get more than 8 bits output. The problem is that the data output of the first shift register, which is supposed to be the data input to the second sr, is early by half of a clock cycle relative to the input data. The attached scope picture shows what I mean. The yellow (ch1) line is the clock signal that I generate. The blue line (ch2) is the data that I send to the first 74hc595. The green line (ch4) is the data output that I'm supposed to use as the input for the next shift register. However, because it's early by a half cycle relative to the clock, the data output on the second shift register is wrong.
To be more precise, the output (ch4) data line, is supposed to delay the input data line (ch2) by 8 clock cycles, but from the image you can see it's delayed by only 7.5 cycles, which brings that out of sync.
The device that outputs these signals to the shift register is either an FT232 or an FT2232H (used for the picture attached), both in bit bang mode. It's weird because from my identical boards using this shift register, some have this problem while others don't. I suppose the issue is because of some impedance mismatch, but I don't know how to solve it. I do place filtering capacitors (0.1uF) at VCC.
Thanks,
Matt