santumevce1412
Junior Member level 2
verilog mux
A 4-to-1 mux using if-else and case is given
if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
# What are the advantages / disadvantages of each coding style shown above?
# How Synthesis tool will give result for above codes?
# What happens if default statement is removed in case statement?
# What happens if combination 11 and default statement is removed? (Hint Latch inference)
pls answer these questions..............
A 4-to-1 mux using if-else and case is given
if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
# What are the advantages / disadvantages of each coding style shown above?
# How Synthesis tool will give result for above codes?
# What happens if default statement is removed in case statement?
# What happens if combination 11 and default statement is removed? (Hint Latch inference)
pls answer these questions..............