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3rd order butterworth bandpass filter corners simulation

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sherif96

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I am designing a 3rd order butterworth bandpass filter whose channel would be 2MHz and between 1MHz and 3 MHz the transfer function derived for the filter is attached with the architecture used to implement, the circuit block is working fine it's response is attached with the circuit itself it consists of 3 stages of OTA-c cells each stage has 3 OTAs, each triangular cell( OTA) is formed of a balanced cascode ota whose circuit is also attached, and the square block is a common common mode feedback circuit between the two middle otas and the last one, I am having a trouble while doing corner simulations, all of them is fine as attached except for the slow slow mode the center frequency has changed from 2 MHz to 1MHz and as you can see the response is no longer flat, I understand that the slow slow operation would change the Vth to be higher which then decreases the resulting current, however what can I do to reverse such operation to reobtain my flat response and correct center frequency?
 

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Have you tried the OTA itself stand-alone for the different corners?
Are all transistors properly biased and operating in their saturation regions, for example, etc.?

I think you should start there first and then plug it into your filter. Also, the CMFB - is that common for quite a few OTAs? I see only a few CMFB circuits.

Also perhaps linebreak your text a bit. It's hard to follow.
 

Have you tried the OTA itself stand-alone for the different corners?
Are all transistors properly biased and operating in their saturation regions, for example, etc.?

I think you should start there first and then plug it into your filter. Also, the CMFB - is that common for quite a few OTAs? I see only a few CMFB circuits.

Also perhaps linebreak your text a bit. It's hard to follow.
Yeah I tried to read my post once again it wasn't intentional to be in that way, sorry about that


-Yes I have tried each OTA for the different corners and plotted the designed gm value, the results of all gm values in corners was identical to the designed value at the typical typical state, attached are the plots for some of the OTAs gm values corner results if you would like to check them out,

- I attached also the ideal circuit where I used voltage controlled current source instead of the OTA it will be easier to follow . There would be one slight modification in the non ideal circuit from the ideal one, I added a fourth ota in each stage parallel to the second OTA because I had differential input and output and the middle OTA is the one where I have my input which resulted in having 4 wires as input to the 2nd ota so the one parallel ota was added.

-Yes all transistors are operating in saturation the cmfb is making sure of that.

-the first ota in each stage has its own cmfb circuit built in the trapezium cell -the one with two inputs only -itself. I added separate CMFB circuit block for the 2nd - including the parallel one- and 3rd OTA - the ones with 3 inputs - because they are all connected to the same differential node so they had to be connected to the same cmfb circuit to avoid having opposing currents.

-I added the corner simulations for the output of each stage, from the 1st stage it is clear that the center frequency is shifted, however all the gm values as attached are the same for all corners , what could be causing this to happen ?

- - - Updated - - -

So what I've figured so far that the shifting in the center frequency could be fixed by decreasing the capacitors value from 5p to 2.5p as attached, however as expected the other corners plots were also shifted the other way, I still could not find a solution for the problem I just figured what was causing the shifting , still no idea how to fix it, the second issue is the response instead of being flat it is decreasing as you can see in the attached picture for the corner results, what could be causing that?
 

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1. The PM0 and PM3 current sources are strangled by cascodes - they has only 100mV of Vds.
2. The CMFB averaging resistors decreases the gain of ota's to ca 30dB - again, if the PM0,3 became in linear you might lose the transconductance. Moreover, the cascodes are useless here, as long as you are killing the output resistance with CMFB resistors.
Separate the CMFB resistors with vcvs acting as ideal buffer.
3. Check if for a problematic corner, the gm of each ota behave similar.
 

Capacitor bank for filter

I am having a trouble with the slow slow corner simulation for my filter- the center frequency is shifted - as attached.

All the capactiors in my filter are 5p F, when I use a 2.5pF the slow slow plot is centered at the correct center frequency once again, so I figured I need to implement a capacitor bank to fix the current issue.

However I still have no idea how to implement one and I do not get the hang of it yet, attached is the bank I think I might need in my circuit based on my understanding, where C1 would be equal to 2.5pF and C2 would be equal to another 2.5pF so when the circuit is closed the total capacitance would be 5p for the regular cases and when the circuit is opened only 2.5p for the slow slow case.

-So my question is would what I just explained be correct?

- would I actually need to exchange all my capacitors with this capacitor bank?

- the control signal which would turn the switch on and off with what should it be connected with to automate the process?
 

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Re: Capacitor bank for filter

( I think the best would be to try to solve the OP-amp/CMFB stories as discussed in your other post. The problem seems to be that one of your components collapse. Did you step through the chain of filter components? Where does the signal misbehave compared to the other corners? Compare "all" nodes for all different corners. Did you try with the ideal CMFB first? )

It is very hard for a circuit to know which corner it is in. There are some process monitors available that could give you some kind of indication of the current corner using some different techniques, but not very reliable, and would require quite some design overhead.

You could also have something on the system level in which your filter is used. It could be used to trim your design and switch in the caps you need to set the frequencies. For example by testing it with a known sine wave at some frequency and then measure the filtered amplitude. But that would require some kind of ADC or similar and once again quite some overhead to fix this.

One could argue that the process corner is static and that the control signal could be set during test and qualification of your device.

If you would have access to those things, your approach sort of seems OK and the control signal would be generated by the process monitor. From a sensitivity point of view, it would make sense to change all capacitors by some deltaC rather than just one.

But as mentioned, I would make the analog design more robust - since I think - you will bump into other issues while extending the testing.
 

Re: Capacitor bank for filter

( I think the best would be to try to solve the OP-amp/CMFB stories as discussed in your other post. The problem seems to be that one of your components collapse. Did you step through the chain of filter components? Where does the signal misbehave compared to the other corners? Compare "all" nodes for all different corners. Did you try with the ideal CMFB first? )

It is very hard for a circuit to know which corner it is in. There are some process monitors available that could give you some kind of indication of the current corner using some different techniques, but not very reliable, and would require quite some design overhead.

You could also have something on the system level in which your filter is used. It could be used to trim your design and switch in the caps you need to set the frequencies. For example by testing it with a known sine wave at some frequency and then measure the filtered amplitude. But that would require some kind of ADC or similar and once again quite some overhead to fix this.

One could argue that the process corner is static and that the control signal could be set during test and qualification of your device.

If you would have access to those things, your approach sort of seems OK and the control signal would be generated by the process monitor. From a sensitivity point of view, it would make sense to change all capacitors by some deltaC rather than just one.

But as mentioned, I would make the analog design more robust - since I think - you will bump into other issues while extending the testing.


I replied on the other post but you didn't, I've done corner simulations on each OTA and they all output the exact designed gm value, shouldn't that indicate that nothing collapses since the circuit is behaving as designed and as it is behaving in all the different corners?

The signal is misbehaving in the output node of all 3 stages , when I simulate corners for the first stage - after the first 3 OTAs- the response is different in the slow slow corner, so I can't figure if the next 2 stages are misbehaving also or not since the 1st stage is already misbehaving, however after simulating each ota in the first stage they all have the same gm value of the different corners.

That's why I figured the best solution for the current problem is to implement a capacitor bank where the capacitor values would adapt to the response based on the control signal and would recenter the slow slow plot at the required center frequency
 

The capacitor bank idea doesn't seem to make sense. If there's a shift in filter parameters due to OTA gm variation, why no stabilize or adjust the OTA?
 

You misunderstood me, I want to implement a capacitor bank because the gm values are actually stable in all corners ,not varying.that is why i excluded the ota having any problems since the output gm is constant in all corners. So now woth knowing that the gms are actually constant do you agree with implementing a capacitor bank to recenter the frequency? And if so i still do not understand the control signal where would it be coming from to automate the process of choosing the correct capacitor values.
 

Re: Capacitor bank for filter

Well, you got the suggestions from the other replies on that post... As mentioned below, I think you should still focus on the OTA.

You can analyze the three different stages by injecting the AC signal at the input of each stage. Break the connections and try them out one by one.

Gm might be OK at DC - but have you checked over the frequencies? I suspect, at slow-slow, the gain-bandwidth is collapsing and feedback cannot be guaranteed. With a 5-pF load, what is the requirement on the bandwidth? Can you alter Gm and reduce capacitance?

Did you have time to check with ideal CMFB?

About the control signal - I mentioned that above. You have to have a process monitor or some mechanism where you test your filter by injecting a sinewave and check where it properly passes the filter. Then you can tell the capacitor to increase/decrease capacitance. Notice that it would be a static signal for each ASIC, not necessarily something that varies over time/operation.
 

Re: Capacitor bank for filter

Well, you got the suggestions from the other replies on that post... As mentioned below, I think you should still focus on the OTA.

You can analyze the three different stages by injecting the AC signal at the input of each stage. Break the connections and try them out one by one.

Gm might be OK at DC - but have you checked over the frequencies? I suspect, at slow-slow, the gain-bandwidth is collapsing and feedback cannot be guaranteed. With a 5-pF load, what is the requirement on the bandwidth? Can you alter Gm and reduce capacitance?

Did you have time to check with ideal CMFB?

About the control signal - I mentioned that above. You have to have a process monitor or some mechanism where you test your filter by injecting a sinewave and check where it properly passes the filter. Then you can tell the capacitor to increase/decrease capacitance. Notice that it would be a static signal for each ASIC, not necessarily something that varies over time/operation.

Attached are screenshots for two examples of AC analysis for the gm value of different OTAs, even the slow-slow corner has the same identical gm value as you can see in the screenshots.

I will try your suggestion of applying an ideal cmfb circuit and comment back to you in a few hours maybe,

The bandwidth I am working on is a 2MHz channel between 1-3 MHz with 2 MHz as center frequency.

I can alter gm value but why would I reduce capacitance value? won't reducing capacitance decrease bandwidth ?
 

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Due to the common-mode feedback and buffer configurations (the right-most feedback circuits in your schematics) (?) you have a loop and then the bandwidth of that loop may play a role. I am referring to the bandwidth of the amplifier as such, not the bandwidth of the filter. Is the loop, in slow-slow, fast enough to support a 3-MHz filter bandwidth?

I think your AC plots are a bit short in terms of frequency. Sweep from 10 Hz to 1 GHz with say 100 points per decade to get a good set of curves of the amplifiers in open-loop and in closed-loop.

The three stages are identical I presume?
 

Due to the common-mode feedback and buffer configurations (the right-most feedback circuits in your schematics) (?) you have a loop and then the bandwidth of that loop may play a role. I am referring to the bandwidth of the amplifier as such, not the bandwidth of the filter. Is the loop, in slow-slow, fast enough to support a 3-MHz filter bandwidth?

I think your AC plots are a bit short in terms of frequency. Sweep from 10 Hz to 1 GHz with say 100 points per decade to get a good set of curves of the amplifiers in open-loop and in closed-loop.

The three stages are identical I presume?

so let me first apologize for clinging on the cap array idea, I figured the gm values should not be constant over different corners as the resulting plots seemed, so I simulated corners again and yes there was a problem while simulating corners, they are not constant , the worst one is the one attached.

I tried simulating with ideal cmfb but as you can see since the otas themselves already fail using ideal cmfb won't make a difference in the current case.

Attached is the a biased ota with desinged output gm of 127.23u, how can I make it insensitive to corner simulation changes? P.S: I removed cascodes.
127.23.PNGnew OTA.PNG
 

I would expect to see some variation in gm over corners, and you have not used any linearization techniques to create a Gm element in your OTA-C (rather than Gm-C).

In the slow-slow corner, I would check if there are any transistors leaving the saturation region (but I think you mentioned they are not?). In addition, you can use a constant-Gm biasing scheme in e.g. the Johns Martin book which might help you tune the current such that gm remains (more) constant over corner. Today, you generate the current as a constant current for the bias? Perhaps you should have a corner-dependent current.

Besides that, to understand the filter, I would suggest to perhaps start a bit from the top: create an OTA model and investigate what requirements you get on bandwidth and current. This could be done with a simple small-signal model containing a vccs and an impedance. This will allow you to understand the impact of gm on the closed response.
 

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