3D IC Design: Is it possible to stack CPU and FPGA?

[manili]

Hi all,
Heterogenous architecture is nothing new at all. We have Zynq family (ARM + Xilinx FPGA), we have Intel's Xeon Scalable processor with FPGA integrated, we have OSFPGA and Caravel in the open-source ecosystem and other SoCs like these. But AFAIK none of these SoCs are using 3D-IC technology which (despite its design challenges) might be led to much better performance/watt/$. So I was wondering to know its possibility at all and if it is possible, why not implemented yet?

Regards

 

[dick_freebird]

You would need some combination of TSVs, interposers, a fortunate alignment of pads to be connected in the Z dimension and a process that can stick all the heterogeneous pieces together. Some of that will be on your tab.

"Can" you? Sure, with enough engineering time, money and determination. "Should" you? That's a business decision and good luck with that; making a case for something so ambitious and with so few examples for cost / risk / opportunity / payback any such analysis must be suspect.

 

[manili]

Thanks Dick,
I appreciate your time to reply but did not find what I was actually looking for, yet. It's not about me, it's about multi-billion dollar R&D teams at Intel and AMD. Is designing such 3D-ICs that impossible for these guys?!

 

[andre_luis]

An IC processor designed to work as a high performance CPU aims for speed and it is designed with internal layout arrangement that optimizes distances between parts as much as possible in order to avoid losses, attenuation and cross interference, so geometry matter a lot; as consequence have to deal with enormous power densities, and the need for a huge coooling engineering; the overall self heating in some sense is the impeditive factor for stacking up anything else nearby.

 

[manili]

Thanks a lot Andre.
I liked the way you replied, so I marked it as the solution/answer. Are there any resources that I can know more about constraints of 3D-IC designing in real world (I am not looking for academic level info and papers)?