16qam modulator implementation

[sagar_eda]

hello all,

i want to implement 16qam modulator on ALTERA STRATIX II FPGA. i am getting input data serially one bit at a time. for 16qam, i need to take 4 bits at a time. these 4 bits serves as address for my LUT to get I and Q values. then i will multiply I and Q values with orthogonal signals (SINE & COSINE) generated using DDS. finally summation of these signals gives my modulated output signal. i have some doubts before starting my implementation. please clarify me.

1. my first problem was how to get 4 bits at a time from input bit stream which is coming 1 bit at a time.
(i know using shift registers, but here i need to wait for 4 clock cycles. is there any other way ? )

2. negative numbers (for 16qam : -1, -3) need to be stored in LUT. do i need to use 2's complement or any other ?

3. i' m thinking of implementing SINE and COSINE signals using DDS(direct digital synthesizer). Is it good method ?

4. how to implement multiplier ? (for multipling I and Q values with SINE and COSINE signals)

5. do i need to add any other blocks (ex-pulse shaping filter) for getting perfect output?

Thanks in advance.

 

[guitarguy12387]

1. Not really... you can't see into the future. Unless your transmitter switches to a 4 bit wide bus.
2. Yes, 2's complement is the most common
3. Yes, DDS is excellent
4. IP core or direct HDL instantiation, depending on your application
5. Not enough info

 

[sagar_eda]

for 2nd question (i.e storing negative numbers in LUT), do i need to use 2's complement or signed magnitude representation ?

 

[lucbra]

two's complement is the most common. If you choose another method, you will need to deal with it. So as long as you are consistent with your choice, you can do whatever you like most.