fikrul
Junior Member level 3
Hello guys,
Does anyone know how to design 16-bit up counter using verilog HDL?
from the binary output produced, it need to be converted into BCD. Then the decimal number will be display at 7-segment. Does anyone know the step/flow should be done for this experiment?
Does anyone know how to design 16-bit up counter using verilog HDL?
from the binary output produced, it need to be converted into BCD. Then the decimal number will be display at 7-segment. Does anyone know the step/flow should be done for this experiment?