kel8157
Full Member level 2
Hi, all
I am using a VHDL testbench and controller, which instantitates a verilog model(non-modifiable). There is an INOUT port. My goal is to make the "Z", "1" or "0" to appear on the signal rom_model.hvlt, without modifying the rom_model.v.
However in NCSIM 08.20-s008, I could only see "U" on the waveform in the testbench, which is not a std_logic value.. And rom_model.hvlt appears unknown.
Attached is the codes and run_sim.csh should run the compilation & simulation.
You may need to modify the cds.lib to include IEEE libs.
Thank you in advance.
:?:
(FYI, in modelsim it's okie)
100 points awarded for the solution!
The rom_model.v shall NOT be modified because it's from client.
I am using a VHDL testbench and controller, which instantitates a verilog model(non-modifiable). There is an INOUT port. My goal is to make the "Z", "1" or "0" to appear on the signal rom_model.hvlt, without modifying the rom_model.v.
However in NCSIM 08.20-s008, I could only see "U" on the waveform in the testbench, which is not a std_logic value.. And rom_model.hvlt appears unknown.
Attached is the codes and run_sim.csh should run the compilation & simulation.
You may need to modify the cds.lib to include IEEE libs.
Thank you in advance.
:?:
(FYI, in modelsim it's okie)
100 points awarded for the solution!
The rom_model.v shall NOT be modified because it's from client.