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Please check the problem , it seems that there is something missing. In general , the condition you have to satisfy to avoid setup time violation is :
Tcq +Tpd +Tsetup < Tclk + Tskew
where Tcq is the Clock-to-Output delay of the first FF, Tpd is the propagation delay, Tsetup is the setup time of the 2nd FF, Tclk is the clock period and Tskew is the skew between the clock arrival times at the two FFs , in the example above Tskew=+2ns. Sometimes ,Tskew may be a negative value.
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