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RAM netlist in HSPICE ?

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bjerkely

bjerkely

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Hi all,

Is it possible to design and simulate a 1 Kbit SRAM array in HSPICE, I mean without connecting each cell manually, is there a function or something else to achieve this in a short way??

Thanx...
 

Hi,
Hspice may be too slow. We did this before via fast spice simulator like Hsim.
 

sunjimmy said:
Hi,
Hspice may be too slow. We did this before via fast spice simulator like Hsim.
Click to expand...

But you have to sacrifice a lot for the accuracy
 

Some simulator like hsim will give you the ability to specify the simulation accuracy and speed on different blocks inside RAM. So you can trade-off the simulation time and accuracy as you like. Sometimes, to reduce the simulation time we will remove the parasitic capacitance manually for functionality check only.
 

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