How to calculate W/L in 0.13um CMOS?

What is new formules to calculate W/L for 0.13um CMOS?

Alan's book (CMOS Analog Circuit Design) give 0.8um design formules, I was told that is out of date, can not be used for 0.13um design.

If you use long transistors in 0.13u you can still use the same old formulas - as long as the short channel effects are not vey pronounced. For shorter channels - well what ever you use will be still inaccurate. You have to adjust by simulation. In this respect I'd use the same formulas to get an approximate sizes of transistors and then use simulations to adjust the schematic.

thanks

thanks.

One more question.

The simulation absolutely did not match the schemetics, how do I modify circuits model of 0.13um, ie, do I have to change lumped R to ditributed R-L-C, and add some R-L-C to NMOS or PMOS lumped model in my schemetics?


thanks.

what do you mean by " the simulation did not match the schematics"? Didn't you run simulation on the schematic? Or you expected different behavior from the schematic than the one you got from the simulation?

oh

What is my mean is that should I add extra parasitic R-L-C to each Gate, Drain, Source of NMOS and PMOS transistors to make them close to real silicon circuits, or I simply use PMOS and NMOS transistor model then simulator will automatically add R-L-C parasitic to my simulation in 0.13um?

At schematic level, pre-layout,
for CMOS, if you are using BSIM, you don't need to add all those prasitic, there are estimated value in the model.

At extracted level, post-layout,
use the extraction tools to extract the parasitic, and do the simulation.

In the previous, I don't get what you mean modify the circuit model? Are you doing RF CMOS? that need to add high frequency component? What model you use? BSIM? EKV? MOS903? etc....

RF IC deisign:

I use Level 28, it is a RF model widely using by industries.

After post simulation, should I add those parasitic components in my original schemetics? And delive THIS modified schemetic to my boss?

If you use a dedicated RF model for the transistors then it should already incorporate in itself the high frequency effects needed for RF design - like gate resistance, may be distributed model of the transistor areas etc. Don't try to modify the model!
You do your pre-layout simulations on the schematic level as you draw it in your schematic editor. Of course, if you want you can put additional capacitors in some sensitive nodes, but those will be only estimates of the parasitics you add from layout. This is based on your judgement. After the layout is done, you extract the parasitics from it and resimulate the design. Usually from layout you get an extracted netlist where you have both the transistors and the parasitics (capacitors and resistors). This netlist is quite different in this respect from the pre-layout netlist. You can use it with your simulator to do the post-layout simulations. I wouldn't advise to backannotate your original schematic with the parasitics - if you do this it'll become a mess. Neither you nor your boss will be able to understand and find your way in the new schematic. However, you can add to the schematic some of the important parasitics in some of the important nodes, which influence the most the functionallity. This way you still have a readable schematic and something that reflects the layout. But always do the post-layout sims on the full extracted netlist from the layout.
Hope this helps.