FPGA - multiple pulse generator

fpga pulse generator

Hi all

I am trying to make an FPGA produce from its IO pins pulses with duty cycle 50%.
The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a
step 1 Hz.

I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to
make the pulse waveform to a sine one so i dont use DAC or memory to write down the pattern.

The accumulators are 32bit and and i have placed a buffer(32 bit) to each one of them just to hold the data. I take the overflow output and drive it to a T flip flop to achieve pulse with a 50% duty cycle.The T ff feeds the IO pin of the FPGA.

I ve found that this block doesnt cost much on gates in the FPGA.
One pulse generator block diagram costs about 70 logic elements on a cyclone II.

Anyway i made this topic because i wan wondering if anyone has a better or easier idea.By any means i want to avoid using PLLs to do something like that.

Thanks in advance

random fpga pulse generator

That works great, if you don't mind the jitter in your output duty cycle.

As an alternative to overflow logic, you could directly output the accumulator's most significant bit. You would also need to divide the increment value by 2, or widen the accumulator by one bit.