Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help!!!!! I want to design a comparator

Status
Not open for further replies.
T

tottistone

Newbie level 4
Joined
Aug 2, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,318
design a comparator

Hello guys, I want to design a comparator with the following restrictions:
Vdd=5V
total quiescent current is 10uA
Vref=4.99V
and the propagation delay should be around 20ns
I do not want to use the dynamic comparator because there is no clock signal in the whole system where the comparator works.
Can anybody give me some suggenstions?
I think the bottlenecks here are the input common mode voltage and the small quiescent current.
Thanks
 

You can use a n differential pair as the pre-amplifier, then follow a latch.
 

the propagation delay should be around 20ns -------I think a common two stage open-loop amplifier worked as a comparator may be meet the 20ns propagation requirment. Actually I simulated one whose propagation is 16ns. But the 10uA current may be too small for the above structure.

the vref=4.99v----You mean the resolution ?
I am just a little puzzled about your description...
 

I agree with jiangnancai that getting 20ns with 10uA power consumption for continue time comparator is impossible. I had 200ns with 20uA on CMOS0.6, but this comparator uses feedback current comparator at the OTA output. Using feedback current comparator allow to improve propagation delay. But it seems to me that 20ns comparator for 5V process will have a hundreds uA power consumption.

What is feedback current comparator u can see at the following reference:
 

u can design the two stage comparator given in Allen holberg, take care of the parameters ur using also please let us know what is Vref.
 

Thansk a lot, guys.
Vref here means that one fixed input of the comparator is 4.99V. That is to say, another input of the comparator will change around 4.99V, as I would like to use this comparator to generate a signal to the logic part of the whole chip.
Acutally, I find that a technique called slew rate enhancement technique, I am trying to apply it in my design. Do you have any comments?
Thanks a lot for your advice.
 

Use the folded-cascode opamp with the n-channel differential pair transistors. This structure can extend the common mode input range beyond the power rail. I think it's difficult to get the speed target of 20ns with the quiescent current of 10uA.
 

Use the folded-cascode opamp ?Yes,it can speed-up the comparator if it is slew rate limited, but this type of structure is impossible to realize with a quiescent current of 10uA.---I think.

May be it needs dynamic operation,any ideas?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top