joskin
Member level 1
Hi,
I'm designing a MASH sigma delta ADC. As you know, if transistor-level clock generator is included in the simulation netlist, the running time will be long. So I used a behavioral clock generator before, and the simulation results show the performance is what I expected.
Unfortunately, when I replace the behavioral clock generator with a transistor-level one, the distortion occurs. The rise/fall time of transistor-level clock generator is smaller than behavioral one.
My question are:
what else should I pay attention to when designing the clock generator?
what does the distortion result from?
I'm designing a MASH sigma delta ADC. As you know, if transistor-level clock generator is included in the simulation netlist, the running time will be long. So I used a behavioral clock generator before, and the simulation results show the performance is what I expected.
Unfortunately, when I replace the behavioral clock generator with a transistor-level one, the distortion occurs. The rise/fall time of transistor-level clock generator is smaller than behavioral one.
My question are:
what else should I pay attention to when designing the clock generator?
what does the distortion result from?
