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How to write a testbench for FFT to generate 2's compliment output?

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fireblade

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hai
iam using fft IPcore to implement on FPGA.
IP Core FFt needs 2's compliment no's as input.
for simulating i am connecting DDS o/p to FFt Input which is also IPCore.
since DDS o/p is not 2's compliment iam not able to get the fft out put correctly.
can any body tell me how can i solve this problem?
if i want write a test bench how can testbench can be written to generate 2,s compliment o/p
 

regarding FFT

What format is your DDS output?
Which language are you using?
 

Re: regarding FFT

fireblade said:
hai
IP Core FFt needs 2's compliment no's as input.
since DDS o/p is not 2's compliment iam not able to get the fft out put correctly.
Click to expand...

Hi,
Why dont you put another module for interfacing that will generate two's complement of the input. :D
 

regarding FFT

hi

As Xtal said keep a module which converts ur DDS o/p to 2's compliment form..............and synchronise the module it will work out .......
 

Re: regarding FFT

try creating a new module if it is in verilog and interface between
 

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