Eugen_E
Full Member level 6
74hc4046
I will design a 2nd order PLL based on the 74HC4046, using the type 2 phase comparator. The loop has to multiply 16x the reference frequency.
The reference signal is derived from a quartz crystal, so it has very low phase noise, but the RC VCO inside the 74HC4046 has high phase noise.
From what I read before, the loop bandwidth, to reduce the VCO phase noise, should be as high as possible, so that the VCO tracks well the reference.
Is this correct? And how to estimate the necesary loop bandwidth?
PS: The reference frequency has a couple of values, so I cant generate directly the frequency needed, using a crystal.
I will design a 2nd order PLL based on the 74HC4046, using the type 2 phase comparator. The loop has to multiply 16x the reference frequency.
The reference signal is derived from a quartz crystal, so it has very low phase noise, but the RC VCO inside the 74HC4046 has high phase noise.
From what I read before, the loop bandwidth, to reduce the VCO phase noise, should be as high as possible, so that the VCO tracks well the reference.
Is this correct? And how to estimate the necesary loop bandwidth?
PS: The reference frequency has a couple of values, so I cant generate directly the frequency needed, using a crystal.