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PLL acquisition problem

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danda821

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HI,

I am designing a CMOS PLL (Tri-state pfd, charge pump, divider, vco). The divider is a swallow divider, so I can choose different dividing ratio (or different channel). It works at the first channel (dividing ratio is 464). But for the highest channel (dividing ratio is 478), it can not lock. The control voltage on VCO settles to 677mV (ripple is 20mV) at 7us, then it randomly increases (ripple goes high to 120mV). Can someone tell me what is the problem? thanks.

danda821
 

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