Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to implement open collector logic in VHDL?

Status
Not open for further replies.

yamaha

Member level 1
Joined
Jan 31, 2007
Messages
38
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Activity points
1,495
hi

how to implement open collector logic in VHDL,

regards
yam
 

Re: Open collector

use and gate
 

    yamaha

    Points: 2
    Helpful Answer Positive Rating
Re: Open collector

If you're interfacing to an external connection that requires open collector characteristics (e.g., PS/2 interface), then you can simulate open collector buffers with 3-state buffers:

out_signal <= '0' when in_signal = '0' else 'Z';
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top