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Soc Encounter design off grid

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ch1pz

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Hi,

When I run a DRC on my design from Encounter in either Tanner L-Edit or Virtuoso I get off grid errors.

The LEF I am using is from the foundry and specifies a manufacturing grid of 0.005. (This is using the TSMC .35u process)

I set up L-Edit using a 0.005 grid as well but it still imports the design off grid.

Is there something I am missing in Encounter that is causing this off grid problem?
When I do a Verify Geometry within Encounter it finds no errors either.

Thanks for your help.
 

Have you used the same TSMC 0.35µ technology to setup Tanner tools? You have to setup the Tanner tool with the appropriate technology files first and then import the design and do DRC. If you dont setup the tool for the technology, it will load the default technology which may be 1.2µ or 0.6µ. This may be the cause of your grid error. When you load the 0.35µ technology file, the grid gets adjusted automatically. Thats what i've observed when using Tanner with different technologies.
 

I do have Tanner set up with the TSMC .35u Tech Setup before I import the GDS file.

The grid that is used in the Tech Setup is 0.025 whereas Encounter's tech file uses 0.005. I have tried Tanner with both grid setups while trying to test the cause of this off grid issue.

If Tanner's grid is at 0.025u you can use the Snap to Manufactering Grid function which does fix these errors, but DRC still has very slight errors.
(Ex: M1 spacing should be 0.45u, but in the design it is 0.446u.)

If Tanner's grid is at 0.005u you can't snap to grid and the DRC violations are present.

I talked to someone at Cadence and they said it may be a rounding issue of some sort.


Thanks for your reply.
 

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