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10 pF capacitor layout

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asdzxc

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How can design a 10 pF capacitor in Cadence with using smallest layout area ?
 

The size of the capacitor will depend of voltage you're gonna put in it. If is low voltage you can use a snwell for you cap but if it is high voltage you probably need to use poly to metal and will consume much more area.
 

how can i design a snwell capacitance I am new at layout design :)
 

The most effective way, that I know is to make chocolate like layout of the Nwell Cap, when the nwell is in shape of square, the Nwell Contact is in the middle of the square. and the poly contracts are at the perimeter of the chocolate array.
In this way you may do abutment from all directions and save area for the Nwell contacts.
The only cons of this layout is rc of poly. So recommended to do maximum width of such array about 50u.
 

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