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Can we merge Verilog and VHDL.......?

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rakesh_aadhimoolam

rakesh_aadhimoolam

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hi folks..........

well day before i attended a seminar on VHDL and Verilog Programming and their usage..........

in that discussion one person made a statement that "as we can merge Verilog and VHDL with respect to eachother..........."blah blah blah

i have this doubt of "Can we merge Verilog and VHDL.......?"

if anyone having an idea..plz share it so.........

and any program based on such would be really useful for everyone...........
 

Many HDL simulators and synthesis tools allow mixing of Verilog and VHDL in the same project, but usually with some limitations. Is that what you meant by "merge"?

For example, here is some info on mixing HDL in Xilinx XST:
**broken link removed**
 

What does merging mean ? if it means to use a mix of verilog and VHDL files in the same project, i think it is ok , but if it means to use them in the same file i do not think this is allowed.
 

At first the IDE should support mixed level programming. Then only you can use both language in single project.
 

If by merge you mean coding a module in verilog (In different file) and instatiate into VHDL in a different file then yes ! There are a lot of simulators which do support mixed mode simulation. FYI calling VHDL entites into verilog modules is also supported.

On the other hand If you mean that you wish to put some verilog and VHDL into a single file and try to simulate this then NO your vhdl/ verilog compiler will give you a error
 

Merging is possible if you are using different files or different components but you can’t use VHDL and Verilog in the same file.
 

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