prashanthsree
Newbie level 1
nedit veriloga
I am designing DIGITAL PHASE LOCKED LOOP using CADENCE.
I have written VERILOG-A code for the Digital Phase Locked Loop. But the actual problem is :--
1. I am opening Verilog-A window from CIW and editing the verilog code. It is giving `include "constants.vams" instead of `include "constants.h".
2. If I edit the verilog code by Pressing Insert command, I am unable to save the text editor.
3. I am read in Cadence tutorial that after saving the verilog-A code it will generate the errors and it will automatically displays the block diagram of the code.
4. How to delete the swap file .. For editing the text editor file again it is showing the message that swap file is created and it should be deleted..
I am designing DIGITAL PHASE LOCKED LOOP using CADENCE.
I have written VERILOG-A code for the Digital Phase Locked Loop. But the actual problem is :--
1. I am opening Verilog-A window from CIW and editing the verilog code. It is giving `include "constants.vams" instead of `include "constants.h".
2. If I edit the verilog code by Pressing Insert command, I am unable to save the text editor.
3. I am read in Cadence tutorial that after saving the verilog-A code it will generate the errors and it will automatically displays the block diagram of the code.
4. How to delete the swap file .. For editing the text editor file again it is showing the message that swap file is created and it should be deleted..
