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need your help about pipeline ADC

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wdd

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Hi,
I'm designing a two channel pipeline ADC (TSMC0.13um process, 1.3v voltage)
But with my first stage transient simulation. There is a trouble I cannot handle it.
You can see the transient output curve in attached picture.
The green one is pre-layout sim, the yellow one is post-layout sim.
Idealy the settling value should be ±500mv, but in post-layout sim there is a -2mv
shift so the value is 498mv and -502mv.
I think it's not mismatch caused, but I have no idea on how it's arised.

Wish your help
wdd
 

Hi,
Why your output of first stage is like that?
Anyway,there is a phase shift between both of your ouput in your post-layout simulation. So maybe you can check your layout for sure if the RC delays is consistent in 'outp'and 'outn'.
 

jeffsky520 said:
Hi,
Why your output of first stage is like that?
Anyway,there is a phase shift between both of your ouput in your post-layout simulation. So maybe you can check your layout for sure if the RC delays is consistent in 'outp'and 'outn'.
Click to expand...

Hi, jeffsky520
My first stage is an opamp-sharing stage, so each phase have an output.
what do you mean of phase shift? how does it affect settling value
btw: my post netlist have parasitic cap no parasitic res.

Best regards,
wdd
 

Your circuit have setlled. Did you check you common voltage is zero in post simulation?
 

jerryzhao said:
Your circuit have setlled. Did you check you common voltage is zero in post simulation?
Click to expand...

Yes, the common offset is OK
I'd found the reason, there is a parasitic coupling cap not match in *.spf file. (it's a clock line, so charge injection causes shift)

Thanks, guys
 

Common-mode voltage variation can not bring error with your output because of differential structure.
Yes, parasitic cap mismatch with two path can shift output., in other words, phase difference is not 180 degree, means that there is a phase shift in both of output.
 

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