siva_7517
Full Member level 2
Hi,
I am doing a semi-custom design asic design. For the back end tool, i have used
First Encounter. Eventually, in this tool i only can see a black box of the standard cell of the design. So, I have import it to virtuoso, to see the transistor level of the design and do the DRC check. But when i do the DRC check in virtuoso, there is DRC error almost in every standard cell. From my view, every standard cell should be clean from DRC but i am not sure why there is a DRC error in standard cell. Can anyone give opinion on this?
Thank you.
Siva
I am doing a semi-custom design asic design. For the back end tool, i have used
First Encounter. Eventually, in this tool i only can see a black box of the standard cell of the design. So, I have import it to virtuoso, to see the transistor level of the design and do the DRC check. But when i do the DRC check in virtuoso, there is DRC error almost in every standard cell. From my view, every standard cell should be clean from DRC but i am not sure why there is a DRC error in standard cell. Can anyone give opinion on this?
Thank you.
Siva